1. Field of the Invention
The present invention relates to a multiplexed text data sampling circuit for use in a data extracting circuit of a multiplexed text broadcasting decoder.
2. Description of the Prior Art
Text broadcasting data (or multiplexed text data) are encoded and multiplexed on a video signal which is included in a television broadcasting wave or which is recorded on a video recording medium such as a laser disk. In general, the multiplexed text data are superimposed on such a video signal during the television vertical blanking interval of the video signal. Then, the multiplexed text data are extracted by a multiplexed text broadcasting decoder built in a television receiver, a multiplexed text broadcasting decoder provided as an adapter, or a multiplexed text broadcasting decoder built in the replay device of a laser disk or the like.
Next, a description will be made as to a prior art multiplexed text data sampling circuit, by taking the data extracting circuit of a captions broadcasting decoder for the hard of hearing that live in the U.S.A., which is referred to as a closed captions decoder, as an example. The multiplexed text data which conforms to the closed captions standard (47CFR .sctn.15.119 and 73.682) are superimposed as a closed captioning signal shown in FIG. 9 on the 21th scanning line during the vertical blanking interval. As shown in FIG. 9, on the 21th scanning line, there exists a clock run-in interval CRI which consists of a 7-cycle sinusoidal burst, a start bit SB, followed by 16 data bits DB, after a back porch period of time.
Referring now to FIG. 10, it illustrates a block diagram showing the structure of the prior art multiplexed text data sampling circuit for use in the data extracting circuit of the closed captions decoder. In the figure, reference numeral 1 denotes a pre-sampling clock generating circuit for generating a pre-sampling clock signal PSCK from a clock signal CK, 2 denotes a start bit detecting circuit for detecting the start bit SB included in a text broadcasting signal and then delivering a start bit detecting signal when detecting the start bit, 9 denotes a sampling clock generating circuit for generating a sampling clock signal SCK to sample the data bits DB included in the text broadcasting signal in response to the start bit detecting signal from the start bit detecting circuit 2, and 10 denotes a data register for capturing the data bits DB in synchronization with the sampling clock signal SCK.
Next, a description will be made as to the operation of the prior art multiplexed text data sampling circuit with reference to timing charts shown in FIGS. 11a to 11e. A signal processing circuit (not shown in FIG. 10) of the multiplexed text broadcasting decoder extracts vertical and horizontal synchronizing signals from a video signal. An AFC (automatic frequency control) circuit stabilizes each of these extracted signals. A count circuit (not shown in the figure) disposed within the multiplexed text broadcasting decoder can find the position of the 21th scanning line included in the video signal by counting the number of pulses of the horizontal synchronizing signal, the counting operation being triggered by the vertical synchronizing signal. A binary encoding circuit (not shown in the figure) converts the signal on the 21th scanning line into a digital signal by comparing the level of the signal on the 21th scanning line with a reference voltage. Hereinafter, the digital signal is referred to as data SDA. The video signal on the 21th scanning line and data SDA are shown in FIGS. 11a and 11b, respectively.
The data SDA are applied to the sampling circuit, as shown in FIG. 10. A clock signal CK of given frequency is also supplied to the sampling circuit. The frequency of the clock signal CK is, for example, twenty times as high as that of the data SDA. The pre-sampling clock generating circuit 1 generates a pre-sampling clock signal PSCK, the phase of which is synchronized with the phase of the data SDA that appear during the clock run-in interval CRI. For example, if the clock signal CK is delivered by the AFC circuit and is synchronized with the horizontal synchronizing signal or pulses that appear during the clock run-in interval CRI, the pre-sampling clock generating circuit 1 can easily generate the pre-sampling clock signal PSCK by dividing the clock signal CK. In the example shown in FIG. 11c, the frequency of the pre-sampling clock signal PSCK is two times as high as that of the pulses that appear during the clock run-in interval CRI. Furthermore, in the example shown in FIG. 11c, the output of the pre-sampling clock signal PSCK is started from the fourth data period of the data SDA that appears during the clock run-in interval CRI.
The start bit detecting circuit 2 samples the data SDA by using the pre-sampling clock signal PSCK and compares each sampled data with a predetermined value. The start bit detecting circuit 2 detects the start bit SB by determining whether a certain pattern appears in the data SDA. As shown in FIG. 11b, since the digital value of the start bit SB is "1" and there exists a blank period between the clock run-in interval CRI and the start bit SB, a digital "0001" can be defined as the certain pattern, for example. The start bit detecting circuit 2 includes, for example, a 4-bit shift register and a 4-bit comparator, and sequentially stores each sampled data in the shift register. Then, the comparator compares the contents of the shift register with the predetermined value. When the comparator determines that they are equal to each other, the start bit detecting circuit 2 furnishes a start bit detecting signal.
When the start bit detecting signal is delivered to the sampling clock generating circuit 9, it starts to generate a sampling clock signal SCK by dividing the clock signal CK, after a predetermined time elapses. The sampling clock generating circuit 9 sets the dividing ratio between the frequency of the original signal, i.e. the clock signal CK and the frequency of the signal obtained by the dividing, i.e. the sampling clock signal SCK in such a manner that the frequency of the sampling clock signal SCK is equal to the frequency of the data bits DB. Furthermore, the predetermined time is determined such that the sampling timing defined by the sampling clock signal SCK is adjusted so that the sampling for each of the data bit DB is carried out at an earlier time within a period of time during which each bit of the data bits DB is input to the sampling circuit. The sampling clock signal SCK having 16 cycles of pulses is delivered. When the clock signal CK is output by the AFC circuit and is synchronized with the horizontal synchronizing signal or pulses of the data SDA that appear during the clock run-in interval CRI, the sampling clock generating circuit 9 can easily generate the sampling clock signal SCK synchronized with the data bits DB by only dividing the clock signal CK with a predetermined dividing ratio since the data bits DB are synchronized with the horizontal synchronizing signal or pulses that appear during the clock run-in interval CRI.
The data register 10 is constructed of a 16-bit shift register. It samples the data SDA when the state of sampling clock signal SCK changes, for example, at the falling edge of the sampling clock signal. That is, every time the sampling clock signal SCK makes a high to low transition, the data register captures each of the data SDA and shifts its contents. Since the sampling clock signal SCK is synchronized with the data bits DB included in the data SDA, the data register 10 can capture each of the data bits DB sequentially by virtue of the sampling clock signal SCK. Finally, when the sampling clock generating circuit 9 becomes a state of outputting no sampling clock signal SCK, all the 16-bit data bits DB are stored in the data register 10. A circuit disposed in a backward stage of the data extracting circuit of the multiplexed text broadcasting decoder can obtain closed captions data by reading the data from the data register 10.
The reasons why the sampling clock generating circuit 9 sets the phase of the sampling clock signal SCK such that the sampling timing for each of the data bits DB is adjusted so that each sampling is carried out at an earlier time within a period of time during which each of the data bits DB is applied to the sampling circuit are as follows.
When replaying the contents stored in a specific laser disk by using a specific laser disk player, the data width of the last bit (the 16th bit) of the data bits DB on a video signal replayed becomes narrower than its nominal value. Therefore, if the sampling timing for each of the data bits DB is adjusted so that each sampling is carried out in the middle of a period of time during which each of the data bits DB is applied to the data sampling circuit, the margin of a time lag which can be introduced into the sampling timing is decreased. Accordingly, the captions data superimposed on the video signal cannot be extracted properly under certain circumstances.
Furthermore, when the multiplexed text broadcasting decoder receives a television broadcasting wave for use in a CATV system, there is a possibility that unnecessary data called a rabbit ear are mixed into the video signal which was scrambled for maintaining cable security and was descrambled, at the back of the 16th one of the data bits DB. If the sampling timing is adjusted so that each sampling is carried out at an earlier time within a period of time during which each of the data bits DB is applied to the multiplexed text data sampling circuit, there is a possibility that the captions data cannot be extracted properly.
Thus, the prior art multiplexed text data sampling circuit having the structure as mentioned above suffers from disadvantages as follows:
1. Detecting the data bits DB is started when a pre-sampled binary value of the data SDA is coincident with a predetermined value. Then, the output of the sampling clock signal SCK is started. However, if the video signal includes a noise caused by for example a weak electric field, an error occurs in the data SDA and hence the sampling clock signal SCK is delivered to the data register at an earlier time than it is usually delivered. Although the start bit detecting signal must be output at a point Q, for example, if a data error occurs at a point P within the clock run-in interval CRI, as shown in FIG. 12d, the start bit detecting signal can be output at a point R. Since this early output causes the sampling clock generating circuit to start to generate a sampling clock signal SCK with 16 pulses at the point R, the closed captions data cannot be captured properly.
2. In general, the prior art multiplexed text data sampling circuit is susceptible to ghost interference before and after the video signal varies. Since the sampling timing is adjusted such that the sampling for each of the data bits DB is carried out at an earlier time within a period of time during which each bit is applied to the sampling circuit, the process of capturing the data bits DB is susceptible to ghost interference. On the contrary, if the sampling timing is shifted in time away from the middle of a period of time during which each of the data bits is applied to the sampling circuit, the process of capturing the data bits DB can be susceptible to a noise caused by, for example, a weak electric field. This increases the possibility of capturing wrong closed captions data. When closed captions data cannot be captured properly, wrong captions are displayed on television.